Conventional CMOS imager sensors read out a row of pixel values at a time to increase the read-out bandwidth, with a row of pixel values digitized in parallel by means of an ADC provided for each pixel column. Such conventional imaging sensor ADCs are illustrated in U.S. Pat. No. 4,851,839 to Reinke, U.S. Pat. No. 5,613,156 to Katayama, and U.S. Pat. No. 5,461,425 to Fowler, et al. Typically, these ADCs comprise a comparator with one of the comparator inputs connected to the bit line of the pixel and the other input connected to a reference signal that is a ramp signal. At every clock cycle, the bit line of the pixel is compared to the reference signal. Initially, the reference signal is less than the pixel signal (e.g., the bit line value), and thus the comparator generates a "0" output value. When the ramp reference crosses the pixel signal, then the comparator generates a `1`, indicating a valid value of the pixel data. This crossover indicates that a valid value of the pixel signal is latched by a register which is typically coupled to the output of the comparator.
Conventional ADCs, however, suffers a shortcoming of causing large power dissipation. A row of ADC comparators is continuously switching at every clock cycle resulting in significant power consumption, particularly when the number of comparators needed increases with the size of the image sensors, with some large format sensors now requiring greater than a thousand comparators. Moreover, the continuous switchings of the comparators result in much wasted power since only switchings around the crossover point are particularly relevant. Thus, there is a need for a lower power ADC architecture for CMOS image sensors.